The present disclosure herein relates to a memory system including a semiconductor memory device, and more particularly, to a flash memory system performing an interleaving operation.
Typically, semiconductor memory devices are classified into volatile memories such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) and nonvolatile memories such as Electrically Erasable Programmable Read-Only Memories (EEPROMs), Ferroelectric Random Access Memories (FRAMs), Phase change Random Access Memories (PRAMs), Magnetoresistive Random Access Memories (MRAMs) and flash memories. Nonvolatile memories lose stored data when power supply is stopped, but nonvolatile memories retain stored data even when power supply is stopped. Particularly, flash memories have advantages of high programming speed, low power consumption, and large-capacity data storage. Accordingly, flash memory systems including flash memories are being widely used as data storage media.
In order to meet excellent performance and low price demanded by consumers, it is required to increase the degree of integration of flash memories. However, there is a limitation in increasing the degree of integration on the manufacturing process of typical two-dimensional flash memories. To overcome such a limitation, three-dimensional flash memories have been proposed. Three-dimensional flash memories are manufactured by vertically stacking multiple layers and forming channel holes. However, it is very difficult to uniformly form channel holes in the three-dimensional flash memories. If the section of the channel hole of the three-dimensional flash memory is not uniform, the frequency of bit error occurrence may be changed between different word lines. Such bit error imbalance also may be an issue for two-dimensional flash memories.